sample hold circuit
英 [ˈsɑːmpl həʊld ˈsɜːkɪt]
美 [ˈsæmpl hoʊld ˈsɜːrkɪt]
网络 保持电路; 取样保持电路
双语例句
- On the basis of analyzing the common methods of background magnetic field compensation, a new automatic compensation method based on sample and hold circuit is put forward.
在分析磁通门常用背景磁场补偿方法基础上，提出一种新的采样保持电路自动补偿方法。 - Design of Sample/ Hold Circuit for High-Speed 14-Bit A/ D Converter
一种用于高速14位A/D转换器的采样/保持电路 - A High Performance CMOS Sample and Hold Circuit
一种高性能CMOS采样/保持电路 - A Method of Background Magnetic Field Compensation for Fluxgate Sensors Based on Sample and Hold Circuit
采样保持电路法补偿磁通门传感器背景磁场 - High Performance Sample and Hold Circuit for Pipelined ADC
适用于流水线ADC的高性能采样/保持电路 - Simulation and Analysis of Capacitor Mismatch Error in Sample and Hold Circuit
对采样保持电路中电容失配的误差分析与仿真 - Analysis and measurement of characteristics of correlated clamp sample and hold circuit
相关箝位采样保持（CCSH）电路特性的测量与分析 - For the design of high resolution A/ D converters, the design of the sample and hold circuit is very important. Here the bottom plate technique is employed, which can cancel the charge injection error.
在高分辨率的A/D转换设计中，采样/保持电路的设计也是非常重要的，本设计采用了下极板采样技术，可以有效地避免电荷注入效应引起的信号失真。 - A Fully Differential CMOS Sample and Hold Circuit
一种全差分CMOS采样/保持电路 - A High Speed 、 Low Distortion Sample And Hold Circuit
一种高速、低失真的采样保持电路 - Design of a deep sub-micron full differential sample/ hold circuit
深亚微米全差分采样/保持电路设计 - The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/ D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。 - A high performance CMOS sample/ hold circuit is presented, which achieves 90-dB spurious-free dynamic range and 80-dB signal-to-noise ratio over Nyquist band in 60 MHz sampling frequency at 3 V supply.
介绍了一种高性能CMOS采样/保持电路。该电路在3V电源电压下，60MHz采样频率时，输入直到奈奎斯特频率仍能够达到90dB的最大信号谐波比（SFDR）和80dB的信噪比（SNR）。 - Consisting of three folded-cascode amplifiers, the op-amp can be used in the sample and hold circuit for a 12-bit, 30 MHz pipelined A/ D converter.
该放大器由三个折叠式共源共栅运算放大器组成，可用于12位40MHz采样频率的流水线A／D转换器。 - A low distortion, high speed switched capacitor sample and hold circuit has been designed. A novel bootstrapped switch is used to degrade the nonlinearity and the method to decrease the settling time of the amplifier is proposed.
设计了一种低失真、高速的开关电容采样保持电路，采用了新型的bootstrapped开关来降低由于开关引入的非线性，并提出了减小放大器的建立时间以减小运算放大器引入的非线性的方法。 - A Sample/ Hold Circuit for 10-Bit 100 MS/ s Pipelined A/ D Converters
用于10位100MS/s流水线A/D转换器的采样保持电路 - The Design of Low Distortion High Speed Sample/ Hold Circuit
低失真与高速采样保持电路的设计 - The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。 - The column output circuit is realized by double sample and hold circuit which can effectively decrease FPN ( fixed pattern noise).
列输出电路采用双采样电路，该电路能有效地消除固定模式噪声。 - Sample and hold circuit ( S/ H) is a critical module in pipelined ADC, which is located at the beginning of the signal processing chain. Its speed and resolution restrict the maximum conversion rate and maximum resolution of the ADC.
采样保持电路是流水线型ADC中的关键模块。它位于转换器信号处理链的最前端，它的速度和分辨率决定了整个转换器所能达到的最大转换速度和最高分辨率。 - Sample/ Hold Circuit ( S/ H) is the most forward part of Pipeline ADC, and its speed resolution and power consumption will mostly determine the performance of the whole ADC.
而采样保持做为流水线型ADC的最前端部分，其速度、精度和功耗将决定着整体ADC的性能。 - In such data conversion system as analog to digital converter, sample/ hold circuit is used to deal with the output signal from anti-aliasing pre filter.
在ADC这样的数据转换系统中，采样／保持电路用于处理从前置抗混叠滤波器输出的信号。 - Important blocks such as the Sample and Hold circuit are analyzed in detail.
详细讨论了采样保持电路等核心单元的设计。 - A detailed description on the development of explosion flame temperature system of hardware and software was given. The hardware circuit mainly includes I/ V conversion circuit, three-stage amplifier, sample and hold circuit, A/ D convert circuit and external expanding memory.
论文详细阐述了该爆炸火焰测温系统的硬件和软件设计，硬件电路主要包括I/V转换电路，三级放大电路，采样保持电路，以及A/D转换电路和外扩存储电路。 - Although this mode can freely adjust integration time, enhance the signal to meet the high-resolution, high sensitivity, high-speed infrared detection needs; but in chip design, the integration amplifier and sample and hold circuit will be contained in a limited area of each pixel.
虽然这种模式可以自由调节积分时间，使信号增强，满足高分辨率、高灵敏度、高速红外探测需求；但是在芯片设计中，要求有限的像元面积内包含积分放大电路和采样保持电路。 - A front-end sample and hold circuit is maintained to ensure the performance when the frequency of the input signal is higher than the nyquist frequency.
为了保证采样高于奈奎斯特频率的输入信号时的线性度，输入端依然采用了采样/保持电路。 - Sample and Hold circuit built-in DAC saves circuit costs and chip area.
采样保持电路内置于DAC，节省了电路开销和芯片面积。 - An amplifier with high slew rate can serve as comparator ( also called single bit analog to digital converter) making up sample/ hold circuit. Adopting high slew rate amplifier is one of the approachs achieving high speed ADC.
具有高压摆率的运放可用作构成采样／保持电路的比较器（或称一位模数转换器）。